The bottleneck has moved to the back end

For three years, the AI supply-chain story has been about who can print the most advanced wafer. That story just changed. Taiwan's ASE Technology, the world's largest chip assembly and test house, has reportedly raised advanced-packaging quotes by more than 20 percent, its steepest AI-driven price hike yet 1. It is a small line item that says something large: pricing power in the AI chip stack has migrated from the front-end foundries to the back-end packaging houses that used to be treated as commodity subcontractors.

The mechanics are straightforward. A modern AI accelerator is not one chip but a stack, a logic die bonded to high-bandwidth memory on an interposer, assembled through TSMC's CoWoS process or an equivalent. Wafer supply has scaled; packaging has not kept pace. TrendForce now estimates the CoWoS supply-demand gap at roughly 20 percent, narrowing to about 10 percent only by the end of 2026 as new lines ramp 2. Until that gap closes, whoever controls assembly slots effectively controls how many finished AI chips reach the market, regardless of how many wafers a foundry can start.

Why ASE can suddenly say no to discounts

ASE's leverage did not appear overnight. The company lifted its 2026 capital budget to a record 8.5 billion dollars in April, up from 7 billion just two months earlier, specifically to chase advanced-packaging demand that was already outrunning supply 3. Executives have signaled the figure will likely need to be revised upward again before the year is out. That is the tell: when a subcontractor raises capex twice in a quarter and still cannot commit to a firm price, it has stopped competing on cost and started allocating scarcity.

TSMC itself is the biggest source of that scarcity. Monthly CoWoS capacity is on track to reach 120,000 to 140,000 wafers in 2026, with another 50,000 to 60,000 wafers coming from outsourced partners like ASE and Amkor, pushing industry-wide capacity toward 200,000 wafers a month 2 7. Even at that scale, Nvidia alone is estimated to have locked up close to 60 percent of CoWoS output for its Rubin and Vera platforms, leaving AMD, Broadcom, Google, and every other accelerator designer to fight over what remains 8. When the anchor customer absorbs most of the capacity increase, the marginal buyer, not the market leader, is the one who pays the new premium. That marginal buyer is now paying ASE's 20 percent.

Amkor's Arizona bet turns the squeeze into policy

The same scarcity is now being built into US industrial policy. Amkor broke ground on a 7 billion dollar advanced-packaging and test campus in Peoria, Arizona, its investment already revised up by 5 billion dollars from the original plan, with production not slated until early 2028 4. In May, Amkor added another 67 acres next to that site and confirmed it is now working with AMD there, alongside previously disclosed commitments to Nvidia and Apple 4 6. CNBC has reported that TSMC's own US packaging expansion is being built explicitly around Nvidia's needs, with Intel's EMIB and Foveros technologies drawing fresh interest from chipmakers unwilling to wait in the CoWoS queue 5.

That is a meaningful second-order effect for Asia's supply chain. The industry is not just adding packaging capacity, it is diversifying who supplies it, geographically and technologically, precisely because the current concentration in Taiwan has become a single point of failure investors and customers alike are pricing as a risk. A 2028 completion date, however, means the current squeeze is a multi-year phenomenon, not a quarter to be waited out.

Reading the trade

For investors, the shift changes where in the AI stack the margin actually sits. ASE's advanced-packaging and test revenue is on pace to roughly double in 2026, and its willingness to push price rather than chase volume suggests management believes this demand is structural, not a cyclical spike to be discounted away once memory and logic supply normalize 1 3. Powertech Technology and other second-tier OSATs absorbing overflow orders from TSMC face the same dynamic on a smaller scale, and are likely to see utilization and pricing follow ASE's lead through the rest of 2026.

The risk case is straightforward: TrendForce's own numbers show the gap narrowing, not widening, and TSMC's roadmap toward a CoPoS panel-level packaging process, targeting pilot production by mid-2027, is designed explicitly to break the CoWoS bottleneck rather than manage it indefinitely 2. Pricing power built on scarcity erodes once the scarcity does. For now, though, the 2026 data points all run one direction: packaging capacity, not wafer starts, is the line item setting the pace of the AI buildout, and Asia's assembly houses are the ones writing the invoice.

For portfolios positioned around the AI supply chain, that argues for weighting OSAT and packaging-equipment exposure alongside the foundry and memory names that have dominated the narrative so far, while watching the 2027 capacity ramp as the point at which today's pricing power starts to fade.