Investors spent most of 2026 watching two AI chip shortages: TSMC's CoWoS advanced-packaging lines and high-bandwidth memory. Both are real constraints. But a third chokepoint has been building quietly behind them, and the earnings and capital-spending numbers coming out of Japan and Taiwan over the past five months say it may now be the tighter one: chip testing.

The Number Nobody Modeled

Advantest, the Tokyo-listed maker of the automated test equipment that screens finished AI chips before they ship, posted record first-quarter revenue of roughly 367.5 billion yen and record operating profit of roughly 190 billion yen for the quarter through June 1 2. A strong quarter alone would not be unusual. What stood out was what came next: Advantest raised its full-year operating profit forecast for the fiscal year ending March 2027 by 34.8%, from 627.5 billion yen to 846 billion yen, and lifted its revenue forecast from 1.42 trillion yen to 1.714 trillion yen 2. The company's explanation was blunt — orders to test AI inference chips had already outrun the assumptions it had built into guidance just three months earlier 1. Equipment makers rarely revise full-year guidance upward mid-cycle; doing so twice in four months signals a backlog problem, not a one-off order.

Taiwan's Test Houses Are Making the Same Bet

Advantest sells the machines. Taiwan's pure-play test houses run them, and they are spending at a pace that suggests they see the same shortage. King Yuan Electronics (KYEC), Taiwan's largest independent chip tester and a key supplier to Nvidia and Broadcom, posted record first-quarter 2026 revenue of NT$10.19 billion — the first time it cleared the NT$10 billion mark in a single quarter — and used the results to raise its 2026 capital budget from a previously approved NT$39.4 billion to NT$50 billion, a roughly 27% increase and a new company record 3. Three months later, KYEC went further still, approving up to US$1.4 billion for its first US testing plant, effectively betting that customers now want test capacity sited outside Asia entirely, not just more of it inside Taiwan 4.

KYEC is not spending alone. TrendForce estimates Taiwan's three largest OSAT testers — ASE, Powertech, and KYEC — will collectively post roughly NT$370 billion in capital expenditure in 2026, a third consecutive record year 5. ASE broke ground in April on a new testing-focused facility in Kaohsiung's Renwu Industrial Park carrying an investment above NT$108.3 billion, explicitly aimed at AI, HPC, 5G, and automotive test demand, with the first phase due by April 2027 and the second by that October 6.

Why Testing, Specifically, Is the Chokepoint

The logic is structural rather than cyclical. As AI accelerators pack more compute, more memory dies, and more advanced packaging into a single part, each chip needs more distinct test insertions — wafer probe, final test, and increasingly system-level test that exercises the whole assembled package under real workloads — and each insertion takes longer to run than it did on a simpler chip. KYEC president Gauss Chang described the shift in August as testing moving from being merely a step in the supply chain to becoming part of the design process itself, with equipment makers, materials suppliers, test houses, and chip designers now co-developing test programs before a chip is even taped out — an integration KYEC calls its four-way model 7. The distinction matters for where the risk sits: a packaging line running under capacity delays a shipment, but a test floor running short strands finished, expensive silicon that has already absorbed the cost of the wafer, the memory, and the packaging around it.

The Spending Is Regional, Not Just Taiwanese

The same test-and-package capacity race is playing out across the wider region. TrendForce tracked Samsung committing roughly $4 billion to a new packaging-and-testing plant in Vietnam and Amkor accelerating its own Vietnam build-out as part of a 2026 capital budget of $2.5 billion to $3 billion 6. In China, JCET broke ground in June on a new advanced-packaging-and-testing facility in Shanghai's Lingang area carrying a 7.8 billion yuan (roughly $1.15 billion) investment, aimed at AI servers, HPC, and GPU packaging, with the first phase due online in the second half of 2028 8.

What It Means for Investors

Three implications follow. First, pricing power is shifting toward the test layer of the supply chain. Advantest and KYEC both raised full-year guidance mid-cycle rather than at the start of a fiscal year, an unusual pattern for equipment and service suppliers that typically sandbag early estimates — it suggests customers are absorbing higher prices and longer lead times rather than pushing back. Second, most of the capacity now being funded will not arrive quickly: ASE's Kaohsiung plant phases in through late 2027 and JCET's Shanghai line targets 2028, which means today's test bottleneck has more than a year left to run independent of how fast underlying AI chip demand itself grows. Third, test capacity is diversifying geographically the same way fabrication and packaging already have — Taiwan remains the center of gravity, but Vietnam, the United States, and Shanghai are all adding meaningful capacity outside the traditional Taiwan-Japan axis, a hedge against the same geopolitical exposure that has already reshaped where chips get packaged.

For investors tracking the AI hardware trade past its most obvious names, the test floor is where the next capacity numbers worth watching will come from — not wafer starts, not HBM allocation, but how many finished chips a tester can push through in a shift.