TSMC Can't Package Its Own Chips Fast Enough. ASE, Amkor and JCET Are Building the Overflow.
By Michele De Filippo
A close-up inside a semiconductor packaging cleanroom: a robotic arm precisely lowering a graphite-grey chip module onto a green substrate carrier on an automated assembly line, rows of finished AI accelerator packages queued behind it under sharp industrial light, shallow depth of field, photographic realism.
20 Aug 2026

The so-what

For three years, the AI chip shortage story has been about wafers: who can etch a 3-nanometer die, and how many. That story is ending. TSMC now says it will hand off a core front-end step of its CoWoS advanced-packaging process to outside assemblers for the first time, a move reported this month and read across the industry as confirmation that packaging, not lithography, is now the binding constraint on how many AI accelerators reach Nvidia, AMD and the hyperscalers 2. The capex race investors have tracked for two years inside TSMC's Hsinchu fabs is now splitting across three outside packaging houses in Taiwan, Arizona and Shanghai, and each is placing a different bet on how long the shortage lasts.

The bottleneck moved

CoWoS, TSMC's chip-on-wafer-on-substrate process, is how a GPU die gets stacked next to its high-bandwidth memory into a single package. It has been the industry's tightest choke point since 2024, and TSMC has already been routing overflow work to outside packagers Amkor and SPIL under license for more than a year 3. What changed this month is that TSMC is reportedly outsourcing the chip-on-wafer bonding step itself, not just the final assembly, because its own lines cannot scale fast enough even as monthly CoWoS capacity climbs toward 130,000 to 140,000 wafers by year-end 2 3. Nvidia alone is estimated to be drawing roughly 60 percent of that global capacity for 2026, leaving everyone else, from custom ASIC designers to AMD, competing for what is left 3.

Three companies, three bets

ASE Technology, the worlds largest chip packaging and testing provider, raised its 2026 capital budget for the second time this year, up another 2 billion dollars to a record 10.5 billion, with 6.5 billion of that going into production equipment for its leading-edge advanced packaging line 1. Management told analysts on last weeks earnings call that the constraint is not finding customers, its building capacity fast enough to serve them, and it is targeting a doubling of leading-edge packaging revenue by 2027 8 1.

Amkor is making the same bet from a different geography. The Arizona-based OSAT posted record second-quarter revenue of 1.9 billion dollars, up 26 percent year over year, with computing revenue climbing 20 percent sequentially on AI data-center demand, and it just added another 67 acres next to its Peoria, Arizona campus to expand what will be the first high-volume advanced-packaging OSAT site in the United States 5 6. Amkor has also signed a ten-year advanced-packaging agreement with TSMC and a separate multi-year infrastructure deal with Nvidia directly, effectively locking in demand before the capacity exists 5.

The third bet is coming from inside China. JCET, the countrys largest OSAT and the worlds third largest overall, is spending roughly 1.4 billion dollars this year on AI-driven advanced packaging, including a new 1.15-billion-dollar plant in Shanghais Lingang zone aimed at domestic AI computing chips that cannot rely on TSMC, Amkor or ASE at all because of export controls 4 7. JCET is chasing a structurally different customer base than the other two, but the capital intensity is the same, and it confirms that packaging capacity is now a national-security line item in China, not just a margin lever 7.

Why TSMC is giving this away

Outsourcing a step it has guarded for years is not generosity. TSMC's foundry economics reward keeping high-margin packaging in-house, but its equipment lead times do not bend to demand the way its outsourcing decisions can. Reported CoWoS assembly lead times have stretched toward 52 to 78 weeks, meaning an order placed today may not ship until well into 2028 on TSMC's own lines 3. Splitting the front-end bonding step out to OSAT partners is the fastest lever TSMC has to narrow a supply-demand gap that industry estimates put at roughly 20 percent for 2026, without waiting years for its own new packaging fabs to ramp 2 3. It also means TSMC is transferring some of the operational risk, and a slice of the revenue, to Amkor, ASE and SPIL, who now carry qualification and yield responsibility for a process step that used to sit entirely inside TSMC's own walls.

The investor read

The practical effect is that AI hardware exposure is no longer a single-stock TSMC or Nvidia trade. It has fragmented across a set of OSATs with genuinely different risk profiles: ASE is the scale incumbent defending share with the deepest capex, Amkor is the US-onshoring beneficiary with contracts that lock in volume years out, and JCET is the sealed-off domestic option serving a China AI stack that increasingly cannot buy Western packaging capacity at any price. Each is now booking record capital budgets against the same underlying scarcity, which means the packaging step of the AI supply chain, long treated as a commodity finishing process, is starting to command the pricing power that used to belong to the fabs alone. Watch utilization and lead-time data from all three over the next two quarters; a narrowing lead time is the signal that the bottleneck has genuinely eased, while a widening one means TSMC's outsourcing move bought time rather than capacity.

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